According to the studies carried out by the present inventors with respect to the manufacturing technique of the semiconductor device, since a degree of integration and a performance of the semiconductor device are enhanced by a proportional reduction of a device dimension, for example, in the manufacture of the semiconductor device, a microfabrication of the device dimension has been advanced year by year. In the advancement of such a microfabrication process technique, it has been increasingly important to reduce a variation of the dimension of the circuit pattern formed on the substrate wafer for stability of electric performance of the semiconductor device. More particularly, since a variation of a gate dimension of a transistor causes a variation of a threshold voltage of the transistor, the variation of the gate dimension of the transistor is required to be severely managed.
As described above, under circumstances where a reduction of the dimensional variation of the circuit pattern formed on the substrate wafer becomes important, techniques and the like disclosed in, for example, Patent Documents 1 to 4 are proposed with respect to the manufacturing technique having the exposure process forming the circuit pattern on the semiconductor device.
In Patent Document 1, different resist patterns are formed in a region having differences in height on the substrate wafer for measuring a focus shift amount with high accuracy in the exposure processing, and a shift amount of a focus position is measured from a difference between these resist dimensions (CD).
In Patent Document 2, by utilizing phenomenon in which the changes of the resist dimensions are different when the exposure dose and the focus condition change depending on a pattern density, two types of resist shapes for the focus measurement which are different in the pattern density are formed on the substrate wafer to measure the shift amount of the focus position by its measurement result of each of the resist dimensions.
In Patent Document 3, the resist dimension of the wafer to which the exposure processing is performed with previously changing the focus condition is measured by scatterometry to determine the optimum focus position from its measurement result, and then, to transmit a focus offset value to exposure device, thereby controlling the focus position.
In Patent Document 4, information related to a wafer is measured and is written in an IC tag attached on the wafer, and then, the information related to the wafer is read from the IC tag in the exposure processing, and the exposure processing is performed based on this read information.    [Patent Document 1] Japanese Patent Application Laid-open Publication No. 2006-30466    [Patent Document 2] Japanese Patent Application Laid-open Publication No. 2005-109016    [Patent Document 3] Japanese Patent Application Laid-open Publication No. 2006-128572    [Patent Document 4] Japanese Patent Application Laid-open Publication No. 2007-115784